1. Field of the Invention
The present invention relates to a network device in a packet switched network and more particularly to a system and method of classifying and filtering packets and thereafter determining appropriate actions for processing the packets.
2. Description of the Related Art
A packet switched network may include one or more network devices, such as an Ethernet switching chip, each of which includes several modules that are used to process information that is transmitted through the device. Specifically, the device includes an ingress module, a Memory Management Unit (MMU) and an egress module. The ingress module includes switching functionality for determining to which destination port a packet should be directed. The MMU is used for storing packet information and performing resource checks. The egress module is used for performing packet modification and for transmitting the packet to at least one appropriate destination port. One of the ports on the device may be a CPU port that enables the device to send and receive information to and from external switching/routing control entities or CPUs.
As packets enter the device from multiple ports, they are forwarded to the ingress module where switching and other processing is performed on the packets. Thereafter, the packets are transmitted to one or more destination ports through the MMU and the egress module. According to a current switching system architecture, when the packet enters the switching device, a fast filter processor examines the packet and status information associated with the packet, among others, to identify various outcomes for processing the packet. For example, one of the outcomes may indicate that the packet should be dropped and another outcome may indicate that the packet should be sent to a specific interface. In one implementation, the fast filter processor includes up to 16 predefined masks which are used to select bytes of the incoming packet. The device includes a meter mechanism for measuring how much packet data per a predefined unit of time is entering the device. The results from the metering mechanism may affect the outcome from the fast filter processor.
However, current implementations include one fast filter processor per chip. As such, the fast filter processor is difficult to scale to higher bandwidths and does not classify and/or filter packets across ports. The searching mechanisms of current fast filter processors also do not scale and, as such, will not hold up under increased bandwidth requirements of future devices with multiple 10 GE ports. Additionally, current implementations of the fast filter processor provide for limited memory resources, wherein a separate memory entry is needed for each port. Furthermore, the current fast filter processor performs a binary search on each packet. Thus, the current fast filter processor would take approximately 8 clock cycles for each lookup. Furthermore, some applications might require filtering on bits and/or fields that are further in the packet then the 80 bytes that is used by current fast filter processors. The current fast filter processor is not flexible in the selection of bits with which to filter.